
library ieee;
use ieee.std_logic_1164.all;

package mystd is
	subtype bus32 is std_logic_vector(31 downto 0);		 -- 32-bitna magistrala
	type registerArray is array( 31 downto 0 ) of bus32; -- niz od 32 32-bitna registra
	subtype bus5  is std_logic_vector(4 downto 0);		 -- linija sa 5 bita
	subtype bus6  is std_logic_vector(5 downto 0);		 -- linija sa 6 bita
	subtype bus8  is std_logic_vector(7 downto 0);		 -- linija sa 8 bita
														 -- potrebno zbog upravljacke jedinice														 										 													 
	type stackArray is array(255 downto 0) of bus32; 	 -- stek memorija
  	
	constant LOADinstr	: bus6 := "000000";
	constant STOREinstr	: bus6 := "100000";
	constant MOVinstr	: bus6 := "001000";
	constant MOVIinstr	: bus6 := "101000";
	
	constant ADDinstr	: bus6 := "000100";
	constant SUBinstr	: bus6 := "100100";
	constant ADDIinstr	: bus6 := "001100";
	constant SUBIinstr	: bus6 := "101100";
	
	constant ANDinstr	: bus6 := "000010";
	constant ORinstr	: bus6 := "100010";
	constant XORinstr	: bus6 := "010010";
	constant NOTinstr	: bus6 := "110010";
	
	constant SHLinstr	: bus6 := "000110";
	constant SHRinstr	: bus6 := "100110";
	constant SARinstr	: bus6 := "010110";
	constant ROLinstr	: bus6 := "110110";
	constant RORinstr	: bus6 := "001110";
	
	constant JMPinstr	: bus6 := "000001";
	constant JSRinstr	: bus6 := "100001";
	constant RTSinstr	: bus6 := "010001";
	
	constant PUSHinstr	: bus6 := "001001";
	constant POPinstr	: bus6 := "101001";
	
	constant BEQinstr	: bus6 := "000101";
	constant BNQinstr	: bus6 := "100101";
	constant BGTinstr	: bus6 := "010101";
	constant BLTinstr	: bus6 := "110101";
	constant BGEinstr	: bus6 := "001101";
	constant BLEinstr	: bus6 := "101101";
	
	constant HALTinstr	: bus6 := "000011";
	
	constant NOPinstr	: bus6 := "001111";
	
	
	-- Funkcija kojom se se menja redosled bitova u std_logic nizu
	FUNCTION bit_reverse(oldBus:std_logic_vector) return std_logic_vector; 

end package mystd;  

package body mystd is

	FUNCTION bit_reverse(oldBus :std_logic_vector) return std_logic_vector is 
		variable newBus : std_logic_vector(oldBus'high downto oldBus'low); 
	begin 
		for i in oldBus'high downto oldBus'low loop 
			newBus(i) := oldBus(oldBus'high + oldBus'low - i); 
		end loop;
		
		return newBus; 
	end bit_reverse; 

end mystd;
 







